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LH5P864
FEATURES * 65,536 x 8 bit organization * Access time: 80 ns (MAX.) * Cycle time: 140 ns (MIN.) * Single +5 V power supply * Power consumption: Operating: 440 mW (MAX.) Standby (TTL level): 22 mW (MAX.) Standby (CMOS level): 2.75 mW (MAX.) * Operating temperature: 0 to 70C * TTL compatible I/O * 512 refresh cycles/8 ms (MAX.) * Available for auto-refresh and self-refresh modes * Package: 32-pin, 525-mil SOP DESCRIPTION
The LH5P864 is a 512K-bit Pseudo-Static RAM organized as 65,536 x 8 bits. It is fabricated using silicon-gate CMOS process technology. With its built-in oscillator, it is easy to refresh memories without an external clock.
CMOS 512K (64K x 8) Pseudo-Static RAM
PIN CONNECTIONS
32-PIN SOP TOP VIEW
TEST NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC NC CE2 R/W A13 A8 A9 A11 OE/RFSH A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
5P864-1
Figure 1. Pin Connections for SOP Package
1
LH5P864
CMOS 512K (64K x 8) Pseudo-Static RAM
16 GND 32 VCC A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 A7 A8 A9 6 5 27 26 A0 - A7 ROW ADDRESS BUFFER SENSE AMPS I/O SELECTOR DATA IN BUFFER 13 I/O0 14 I/O1 15 I/O2 17 I/O3 18 I/O4 19 I/O5 20 I/O6 DATA OUT BUFFER 21 I/O7
VBB GENERATOR
A8 - A14
COLUMN ADDRESS BUFFER
COLUMN DECODER
A10 23 A11 25 A12 4 A13 28 A14 3
REFRESH ADDRESS COUNTER
EXT/INT ADDRESS MUX
ROW DECODER
MEMORY ARRAY 256K MEMORY ARRAY 256K
CE1 22 CE2 30
CLOCK GENERATOR
TEST1 1
REFRESH CONTROLLER
REFRESH TIMER
OE/ 24 RFSH R/W 29
5P864-2
Figure 2. LH5P864 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A14 R/W OE/RFSH CE1, CE2 I/O0 - I/O7
Address input Read/Write Enable input Output Enable input/Refresh input Chip Enable input Data input/output
VCC GND Test NC
Power Supply Ground Test Input No Connection
2
CMOS 512K (64K x 8) Pseudo-Static RAM
LH5P864
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Applied voltage on any pin Output short circuit current Power dissipation Operating temperature Storage temperature
VT IO PD Topr Tstg
-1.0 to +7.0 50 600 0 to +70 -65 to +150
V mA mW C C
1
NOTE: 1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage Input voltage
VCC VIH VIL
4.5 2.4 -1.0
5.0
5.5 VCC + 0.3 0.8
V V V
CAPACITANCE (TA = 0 to +70C, f = 1MHz, VCC = 5.0 V 10%)
PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT
A0 - A14 Input capacitance R/W, OE/RFSH CE1, CE 2 TEST1 Input/Output capacitance I/O0 - I/O7
CIN1 CIN2 CIN3 CIN4 COUT1
8 8 8 10 10
pF pF pF pF pF
DC CHARACTERISTICS (TA = 0 to +70C, VCC = 5.0 V 10%)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Operating current Standby current Self refresh average current Input leakage current Output leakage current Output HIGH voltage Output LOW voltage
ICC1 ICC2 ICC3 ILI ILO VOH VOL
tRC = t RC (MIN.) TTL input CMOS input TTL input CMOS input 0 V V IN 6.5 V, 0 V except on test pins 0 V V OUT V CC + 0.3 V, Outputs in High-Z state IOUT = -1.0 mA IOUT = 4.0 mA -10 -10 2.4
80 4.0 0.5 4.0 0.5 10 10
mA mA mA mA mA A A V
1, 2 1, 3, 5 1, 3, 6 1, 4, 5 1, 4, 6
0.4
V
NOTES: 1. Specified values are with outputs open. 2. I CC1 depends on the cycle time. 3. CE1 = CE2 = VIH, OE/RFSH = VIH 4. CE1 = CE2 = VIH, OE/RFSH = VIL 5. CE1 = CE2 = VCC - 0.2 V, OE/RFSH = VCC - 0.2 V 6. CE1 = CE2 = VCC - 0.2 V, OE/RFSH = 0.2 V
3
LH5P864
CMOS 512K (64K x 8) Pseudo-Static RAM
AC CHARACTERISTICS 1,2,3 (TA = 0 to +70C, VCC = 5.0 V 10%)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Random read, write cycle time Read modify write cycle time CE pulse width CE precharge time Address setup time Address hold time Read command setup time Read command hold time CE access time OE access time CE to output in Low-Z OE to output in Low-Z R/W to output in Low-Z Chip disable to output in High-Z Output disable to output in High-Z Write enable to output in High-Z OE setup time OE hold time OE lead time Write command pulse width Write command setup time Write command hold time Data setup time from write Data setup time from CE Data hold time from write Data hold time from CE Transition time (rise and fall) Refresh time interval Auto refresh cycle time Refresh delay time from CE Refresh pulse width (Auto refresh) Refresh precharge time (Auto refresh) CE delay time from refresh precharge (Auto refresh) Refresh pulse width (Self refresh) CE delay time from refresh precharge (Self refresh)
NOTES: 1. In order to initialize the circuit, CE1, CE2 and OE/RFSH should be kept in VIH for 100 s after power-up and followed by at least 8 dummy cycles. 2. AC characteristics are measured at t T = 5 ns. 3. AC characteristics are measured at the following condition (see figure at right). 4. Address is latched at the negative edge of CE1 or CE2. 5. Measured with a load equivalent to 2TTL + 100 pF. 6. Data is latched at the positive edge of R/W or at the positive edge of CE1 or CE2.
tRC tRMW tCE tP tAS tAH tRCS tRCH tCEA tOEA tCLZ tOLZ tWLZ tCHZ tOHZ tWHZ tOES tOEH tOEL tWCP tWCS tWCH tDSW tDSC tDHW tDHC tT tREF tFC tRFD tFAP tFP tFCE tFAS tFRS
140 205 80 50 0 20 0 0 80 30 20 0 0 25 25 25 10 10 10 30 30 50 30 30 0 0 3 130 50 30 30 160 8,000 160 8,000 35 8 10,000
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns 6 6 6 6 5 5 4 4
INPUT
2.4 V 0.8 V
2.6 V 0.6 V 2.2 V 0.8 V
5P864-3
OUTPUT
Figure 3. AC Characteristics
4
CMOS 512K (64K x 8) Pseudo-Static RAM
LH5P864
tRC tP VIH CE1 (OR CE2) VIL VIH CE2 (OR CE1) VIL tAS tAH tCE tP
A0 - A14 VIH VIL
ADDRESS INPUT
tOEH
tOEL
tOES
V OE/RFSH VIH IL tRCS VIH R/W VIL tOEA tCEA tOLZ tCLZ V I/O0 - I/O7 VOH OL tCHZ tOHZ tRCH
VALID-DATA OUTPUT
5P864-4
Figure 4. Read Cycle
5
LH5P864
CMOS 512K (64K x 8) Pseudo-Static RAM
tRC tP VIH CE1 (OR CE2) VIL VIH CE2 (OR CE1) VIL tAS tAH tCE tP
A0 - A14 VIH VIL tOES
ADDRESS INPUT
tOEH
V OE/RFSH VIH IL tWCH tWCS tWCP VIH R/W VIL tDSW tDSC V I/O0 - I/O7 VIH IL tDHW tDHC
VALID-DATA INPUT
5P864-5
Figure 5. Write Cycle
6
CMOS 512K (64K x 8) Pseudo-Static RAM
LH5P864
tRMW tP VIH CE1 (OR CE2) VIL VIH CE2 (OR CE1) VIL tP
tAS
tAH
A0 - A14 VIH VIL
ADDRESS INPUT
tOEH
tOES
V OE/RFSH VIH IL tWCS tRCS tWCP
VIH R/W VIL tDSW tDSC tDHW tDHC
VIH VIL tCEA tOEA I/O0 - I/O7 tOLZ tCLZ tWHZ tOHZ
VALID-DATA INPUT
tWLZ
tCHZ
VOH VOL
VALID-DATA OUTPUT
5P864-6
Figure 6. Read-Modify-Write Cycle
7
LH5P864
CMOS 512K (64K x 8) Pseudo-Static RAM
tRC tP VIH CE1 (OR CE2) VIL VIH CE2 (OR CE1) VIL tAS tAH tCE tP
A0 - A7
VIH VIL
ADDRESS INPUT
tOES VIH VIL tRCS tRCH
tOEH
OE/RFSH
R/W
VIH VIL
HIGH-Z
V I/O0 - I/O7 VOH OL NOTE: A8 - A14 Don't Care
5P864-7
Figure 7. CE Only Refresh Cycle
VIH CE1 VIL V CE2 VIH IL tRFD tFAP tFC tFP tFAP tFCE
V OE/RFSH VIH IL V I/O0 - I/O7 VOH OL NOTE: A0 - A14, R/W Don't Care
HIGH-Z
5P864-8
Figure 8. Auto Refresh Cycle
8
CMOS 512K (64K x 8) Pseudo-Static RAM
LH5P864
VIH CE1 VIL V CE2 VIH IL tRFD tFAS tFRS
V OE/RFSH VIH IL V I/O0 - I/O7 VOH OL NOTE: A0 - A14, R/W Don't Care
HIGH-Z
5P864-9
Figure 9. Self Refresh Cycle
PACKAGE DIAGRAM
32SOP (SOP032-P-0525)
1.27 [0.050] TYP. 1.40 [0.055] 17
0.50 [0.020] 0.30 [0.012]
32
11.50 [0.453] 11.10 [0.437]
14.50 [0.571] 13.70 [0.539]
12.50 [0.492]
1 20.80 [0.819] 20.40 [0.803]
16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
32SOP
32-pin, 525-mil SOP
9
LH5P864
CMOS 512K (64K x 8) Pseudo-Static RAM
ORDERING INFORMATION
LH5P864 Device Type N Package - ## Speed 80 Access Time (ns)
32-pin, 525-mil SOP (SOP032-P-0525)
CMOS 512K (64K x 8) Pseudo-Static RAM Example: LH5P864N-80 (CMOS 512K (64K x 8) Pseudo-Static RAM, 80 ns, 32-pin, 525-mil SOP)
5P864-10
10

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